In recent years, video cameras and electronic cameras have become widespread. As these cameras, CCD-type and CMOS-type image pickup apparatuses (solid-state image pickup apparatuses) are used. The CMOS-type image pickup apparatus refers to an apparatus that guides signal charge accumulated in a light-receiving pixel to a control electrode of a MOS transistor provided in a pixel unit and outputs an amplified signal from a main electrode.
When a dynamic range of a pixel signal is expanded in a CMOS sensor (CMOS-type solid-state image pickup apparatus), a method may be used of enlarging the dynamic range by synthesizing a central pixel and a plurality of pixels in the vicinity of the central pixel. For example, as shown in an example of image weighting of FIG. 18, a pixel R1, a pixel R2, and a pixel R3 of the same color may be weighted and added up. That is, the dynamic range of a signal with respect to a noise may be improved by weighting and adding up (adding up at a fixed ratio) the respective signals levels of a signal Sig1 output through a vertical signal line VL from the pixel R1, a signal Sig2 output through the vertical signal line VL from the pixel R2, and a signal Sig3 output through the vertical signal line VL from the pixel R3.
For example, when the signal level of the signal Sig1 output from the pixel R1 is set to Sig1, the signal level of the signal Sig2 output from the pixel R2 is set to Sig2, and the signal level of the signal Sig3 output from the pixel R3 is set to Sig3, the weighting addition is performed with “weighting addition value=Sig1+2×Sig2+Sig3” or the like.
Meanwhile, when such a weighting addition is performed, a method is used of converting the output signals Sig1, Sig2, and Sig3, which are output from the respective pixels R1, R2, and R3, to digital data (digital values) by an A/D conversion circuit (ADC) within a solid-state image pickup apparatus 1A (within a chip) or an A/D conversion circuit provided outside the apparatus and performing weighting addition using the pixel signals converted to the digital values.
This is for the purpose of temporarily converting the signals Sig1, Sig2, and Sig3 to the digital data and storing the signals in a memory or the like and then performing the weighting addition by using the digital values stored in the memory or the like, because the signals Sig1, Sig2, and Sig3 output from the vertical signal line VL are output in time series without being simultaneously output from the vertical signal line VL.
Meanwhile, there is a related solid-state image pickup apparatus (see Patent Document 1). The solid-state image pickup apparatus disclosed in Patent Document 1 is aimed at providing a solid-state image pickup apparatus including an ADC capable of being disposed in a limited space. In the solid-state image pickup apparatus, signals of pixels output through a vertical read-out line are held as potentials in a node, and a plurality of capacitors are capacitively coupled to the node holding the signals of the pixels. Voltages of counter electrodes of the plurality of capacitors are sequentially switched by controlling a transistor, thereby lowering the potential of the node in a step shape (that is, in a stepwise manner or in a slope shape). A comparator compares the potential of the node with the potentials of the pixels in a dark state, and determines a high-order bit of a digital value when the potential of the node becomes lower. Subsequently, the conversion of a low-order bit of the digital value is started.
In addition, there is a related image pickup apparatus (see Patent Document 2). The image pickup apparatus disclosed in Patent Document 2 is aimed at realizing linearity suited to characteristics of the human eye as much as possible without dynamically changing an accumulation period of a solid-state image pickup element in the image pickup apparatus, and achieving the expansion of a dynamic range. In the image pickup apparatus disclosed in Patent Document 2, a sensor chip outputs image pickup signals in parallel, which are read out from a pixel unit a plurality of times within one frame period, to an N channel within an exposure period shorter than an existing one frame period which is determined as a standard. A frame memory accumulates the image pickup signals corresponding to a plurality of frames. A frame addition circuit adds up signals of a plurality of frames read out from the frame memory to thereby create signals corresponding to a standard one frame. Thus, the dynamic range can be set to the square of N at most.